IGNOU BPHET-143 Solved Assignment 2024 B.Sc (G) CBCS cover page

IGNOU BPHET-143 Solved Assignment 2024 | B.Sc (G) CBCS

Solved By – Narendra Kr. Sharma – M.Sc (Mathematics Honors) – Delhi University

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IGNOU BPHET-143 Assignment Question Paper 2024

bphet-143-solved-assignment-2024–qp-dcdecc01-970e-4444-9909-a661e3e8e6c0

bphet-143-solved-assignment-2024–qp-dcdecc01-970e-4444-9909-a661e3e8e6c0

PART A
  1. a) Write the three processes responsible for charge carrier transport in a semiconductor. Calculate the resistivity of an intrinsic semiconductor sample of area 4 c m 2 4 c m 2 4cm^(2)4 \mathrm{~cm}^24 cm2, thickness 0.5 c m 0.5 c m 0.5cm0.5 \mathrm{~cm}0.5 cm and carrier concentration of 5 × 10 16 m 3 5 × 10 16 m 3 5xx10^(16)m^(-3)5 \times 10^{16} \mathrm{~m}^{-3}5×1016 m3. It is given that the electron and hole motilities are 0.35 m 2 V 1 s 1 0.35 m 2 V 1 s 1 0.35m^(2)V^(-1)s^(-1)0.35 \mathrm{~m}^2 \mathrm{~V}^{-1} \mathrm{~s}^{-1}0.35 m2 V1 s1 and 0.2 m 2 V 1 s 1 0.2 m 2 V 1 s 1 0.2m^(2)V^(-1)s^(-1)0.2 \mathrm{~m}^2 \mathrm{~V}^{-1} \mathrm{~s}^{-1}0.2 m2 V1 s1 respectively.
b) What is the difference between a zener diode and a conventional p n p n p-np-npn junction diode? Explain the breakdown processes observed in case of zener diode.
2. a) Draw the structure of an n-channel JFET and explain the process of pinch-off when appropriate voltage bias is applied. Why is the depletion layer wider near the drain terminal?
b) Design a universal bias for a CE-amplifier (Fig. 4.11 of your study material) using n p n n p n n-p-nn-p-nnpn transistor for the following parameter values: V C C = 20 V , V B = 4 V V C C = 20 V , V B = 4 V V_(CC)=20V,V_(B)=4VV_{C C}=20 \mathrm{~V}, V_B=4 \mathrm{~V}VCC=20 V,VB=4 V, I C = 10 m A , V B E = 0.6 V , V C E = 10 V I C = 10 m A , V B E = 0.6 V , V C E = 10 V I_(C)=10mA,V_(BE)=0.6V,V_(CE)=10VI_C=10 \mathrm{~mA}, V_{B E}=0.6 \mathrm{~V}, V_{C E}=10 \mathrm{~V}IC=10 mA,VBE=0.6 V,VCE=10 V and β = 100 β = 100 beta=100\beta=100β=100. Obtain the values of R C , R E , R 1 R C , R E , R 1 R_(C),R_(E),R_(1)R_C, R_E, R_1RC,RE,R1 and R 2 R 2 R_(2)R_2R2. Explain how the Q Q QQQ-point remains stable in this biasing scheme.
3. a) Convert 732.52 10 732.52 10 732.52_(10)732.52_{10}732.5210 into its octal equivalent.
b) Draw a circuit to realize a 2-input AND gate using two diodes and explain its working with the help of its truth table.
c) Write the Sum of Products (Boolean expression) for the following truth table, simplify it and draw its logic circuit using minimum number of gates.
A A AAA B B BBB C C CCC Y Y YYY
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
A B C Y 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0| $A$ | $B$ | $C$ | $Y$ | | :— | :— | :— | :— | | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 0 |
4 a) Write the truth table of a full adder and obtain the expressions of its Sum and Carry using the SOP method.
b) Draw the circuit of 2’s complement binary adder-subtractor and using it explain the addition of binary equivalent of decimal number 7 and binary equivalent of decimal number 6 .
PART B
5. a) Draw the circuit and explain the working of a class B push-pull amplifier. What are its advantages over a class A power amplifier?
b) Explain the effect of negative feedback on the performance of an amplifier. Calculate the gain of negative feedback amplifier with internal gain A = 500 A = 500 A=500A=500A=500 and feedback factor β = 0.02 β = 0.02 beta=0.02\beta=0.02β=0.02.
6. a) Explain the working of Wien bridge oscillator. Calculate the value of resistors in the Wien bridge oscillator with frequency f = 5 k H z f = 5 k H z f=5kHzf=5 \mathrm{kHz}f=5kHz if 100 p F 100 p F 100pF100 \mathrm{pF}100pF capacitors are used.
b) State the criteria for obtaining sustained oscillations from an oscillator circuit. Draw the circuit of Hartley Oscillator. A Hartley oscillator oscillates with 500 k H z 500 k H z 500kHz500 \mathrm{kHz}500kHz frequency. Determine the total inductance, L L LLL forming the tank circuit with 10 p F 10 p F 10pF10 \mathrm{pF}10pF capacitor.
c) Design a shunt voltage regulator using a zener diode to give regulated 10 V 10 V 10V10 \mathrm{~V}10 V dc output with maximum load current of 100 m A 100 m A 100mA100 \mathrm{~mA}100 mA. Consider that input unregulated dc supply is 15 V 15 V 15V15 \mathrm{~V}15 V and I z = 1 m A I z = 1 m A I_(z)=1mAI_z=1 \mathrm{~mA}Iz=1 mA. Write down the voltage and power ratings of the zener diode and power rating of series resistor R S R S R_(S)R_SRS in your circuit.
7. a) A triangular wave of ± 12 V ± 12 V +-12V\pm 12 \mathrm{~V}±12 V amplitude and 10 M H z 10 M H z 10MHz10 \mathrm{MHz}10MHz frequency is generated at the output of an op-amp. Calculate the minimum slew rate of this op-amp.
b) Design a 3-channel op-amp based circuit to give following output relation:
V o = 7 V 1 5 V 2 + 10 d V 3 d t V o = 7 V 1 5 V 2 + 10 d V 3 d t V_(o)=7V_(1)-5V_(2)+10(dV_(3))/(dt)V_o=7 V_1-5 V_2+10 \frac{d V_3}{d t}Vo=7V15V2+10dV3dt
  1. a) Refer to Fig. 15.4 in your study material showing the geometry of the electron beam deflection in a CRT. In this CRT, the length of the deflections plates ( L ) ( L ) (L)(L)(L) is 4 c m 4 c m 4cm4 \mathrm{~cm}4 cm and the distance between the screen and the centre of the deflection plates ( R ) ( R ) (R)(R)(R) is 10 c m 10 c m 10cm10 \mathrm{~cm}10 cm. Accelerating voltage applied to the anode is 1000 V 1000 V 1000V1000 \mathrm{~V}1000 V and applied deflection voltage is 75 V 75 V 75V75 \mathrm{~V}75 V. If the deflection suffered by the electron beam at the edge of the deflection plate ( h ) ( h ) (h)(h)(h) is 1 m m 1 m m 1mm1 \mathrm{~mm}1 mm, calculate the plate separation (s). Determine the deflection observed on the CRT screen ( y ) ( y ) (y)(y)(y) and calculate the deflection sensitivity.
    b) Design and draw the circuit of a monostable multivibrator using IC 555 timer to generate a pulse of 5.5 s 5.5 s 5.5s5.5 \mathrm{~s}5.5 s duration when a trigger pulse is applied.
\(cos\left(2\theta \right)=cos^2\theta -sin^2\theta \)

BPHET-143 Sample Solution 2024

bphet-143-solved-assignment-2024-ss-8e24e610-06c9-4b43-84f6-a5bf6ef5ab5c

bphet-143-solved-assignment-2024-ss-8e24e610-06c9-4b43-84f6-a5bf6ef5ab5c

PART A
  1. a) Write the three processes responsible for charge carrier transport in a semiconductor. Calculate the resistivity of an intrinsic semiconductor sample of area 4 c m 2 4 c m 2 4cm^(2)4 \mathrm{~cm}^24 cm2, thickness 0.5 c m 0.5 c m 0.5cm0.5 \mathrm{~cm}0.5 cm and carrier concentration of 5 × 10 16 m 3 5 × 10 16 m 3 5xx10^(16)m^(-3)5 \times 10^{16} \mathrm{~m}^{-3}5×1016 m3. It is given that the electron and hole motilities are 0.35 m 2 V 1 s 1 0.35 m 2 V 1 s 1 0.35m^(2)V^(-1)s^(-1)0.35 \mathrm{~m}^2 \mathrm{~V}^{-1} \mathrm{~s}^{-1}0.35 m2 V1 s1 and 0.2 m 2 V 1 s 1 0.2 m 2 V 1 s 1 0.2m^(2)V^(-1)s^(-1)0.2 \mathrm{~m}^2 \mathrm{~V}^{-1} \mathrm{~s}^{-1}0.2 m2 V1 s1 respectively.
Answer:
The three processes responsible for charge carrier transport in a semiconductor are:
  1. Drift: When an electric field is applied to a semiconductor, the charge carriers (electrons and holes) experience a force in the direction of the field. This causes the carriers to drift toward the opposite charges, resulting in a current. The drift velocity of the carriers is proportional to the applied electric field.
  2. Diffusion: In the absence of an electric field, charge carriers move from regions of high concentration to regions of low concentration due to the concentration gradient. This movement is called diffusion and is driven by the random thermal motion of the carriers.
  3. Thermionic Emission: At elevated temperatures, some electrons in the semiconductor gain enough energy to overcome the potential barrier at a junction (e.g., a metal-semiconductor junction or a p-n junction) and are emitted into the adjacent region. This process is known as thermionic emission.
Now, let’s calculate the resistivity of the given intrinsic semiconductor sample.
The resistivity ( ρ ρ rho\rhoρ) of a semiconductor can be calculated using the formula:
ρ = 1 σ ρ = 1 σ rho=(1)/(sigma)\rho = \frac{1}{\sigma}ρ=1σ
where σ σ sigma\sigmaσ is the conductivity of the semiconductor. For an intrinsic semiconductor, the conductivity can be calculated using the formula:
σ = q ( n μ n + p μ p ) σ = q ( n μ n + p μ p ) sigma=q(nmu _(n)+pmu _(p))\sigma = q(n\mu_n + p\mu_p)σ=q(nμn+pμp)
where
  • q q qqq is the elementary charge ( 1.6 × 10 19 C 1.6 × 10 19 C 1.6 xx10^(-19)” C”1.6 \times 10^{-19} \text{ C}1.6×1019 C),
  • n n nnn and p p ppp are the electron and hole concentrations, respectively (which are equal in an intrinsic semiconductor),
  • μ n μ n mu _(n)\mu_nμn and μ p μ p mu _(p)\mu_pμp are the mobilities of electrons and holes, respectively.
Given:
  • n = p = 5 × 10 16 m 3 n = p = 5 × 10 16 m 3 n=p=5xx10^(16)” m”^(-3)n = p = 5 \times 10^{16} \text{ m}^{-3}n=p=5×1016 m3,
  • μ n = 0.35 m 2 V 1 s 1 μ n = 0.35 m 2 V 1 s 1 mu _(n)=0.35″ m”^(2)”V”^(-1)”s”^(-1)\mu_n = 0.35 \text{ m}^2\text{V}^{-1}\text{s}^{-1}μn=0.35 m2V1s1,
  • μ p = 0.2 m 2 V 1 s 1 μ p = 0.2 m 2 V 1 s 1 mu _(p)=0.2″ m”^(2)”V”^(-1)”s”^(-1)\mu_p = 0.2 \text{ m}^2\text{V}^{-1}\text{s}^{-1}μp=0.2 m2V1s1.
Let’s substitute the values:
σ = 1.6 × 10 19 C × ( 5 × 10 16 m 3 × 0.35 m 2 V 1 s 1 + 5 × 10 16 m 3 × 0.2 m 2 V 1 s 1 ) σ = 1.6 × 10 19 C × ( 5 × 10 16 m 3 × 0.35 m 2 V 1 s 1 + 5 × 10 16 m 3 × 0.2 m 2 V 1 s 1 ) sigma=1.6 xx10^(-19)” C”xx(5xx10^(16)” m”^(-3)xx0.35″ m”^(2)”V”^(-1)”s”^(-1)+5xx10^(16)” m”^(-3)xx0.2″ m”^(2)”V”^(-1)”s”^(-1))\sigma = 1.6 \times 10^{-19} \text{ C} \times (5 \times 10^{16} \text{ m}^{-3} \times 0.35 \text{ m}^2\text{V}^{-1}\text{s}^{-1} + 5 \times 10^{16} \text{ m}^{-3} \times 0.2 \text{ m}^2\text{V}^{-1}\text{s}^{-1})σ=1.6×1019 C×(5×1016 m3×0.35 m2V1s1+5×1016 m3×0.2 m2V1s1)
After Calculating we get:
σ = 1.6 × 10 19 C × 2.75 × 10 16 m 1 V 1 s 1 = 4.4 × 10 3 S/m σ = 1.6 × 10 19 C × 2.75 × 10 16 m 1 V 1 s 1 = 4.4 × 10 3 S/m sigma=1.6 xx10^(-19)” C”xx2.75 xx10^(16)” m”^(-1)”V”^(-1)”s”^(-1)=4.4 xx10^(-3)” S/m”\sigma = 1.6 \times 10^{-19} \text{ C} \times 2.75 \times 10^{16} \text{ m}^{-1}\text{V}^{-1}\text{s}^{-1} = 4.4 \times 10^{-3} \text{ S/m}σ=1.6×1019 C×2.75×1016 m1V1s1=4.4×103 S/m
Now, the resistivity is:
ρ = 1 σ = 1 4.4 × 10 3 S/m = 227.27 Ω m ρ = 1 σ = 1 4.4 × 10 3 S/m = 227.27 Ω m rho=(1)/(sigma)=(1)/(4.4 xx10^(-3)” S/m”)=227.27Omega”m”\rho = \frac{1}{\sigma} = \frac{1}{4.4 \times 10^{-3} \text{ S/m}} = 227.27 \text{ }\Omega\text{m}ρ=1σ=14.4×103 S/m=227.27 Ωm
Therefore, the resistivity of the intrinsic semiconductor sample is 227.27 Ω m 227.27 Ω m 227.27Omega”m”227.27 \text{ }\Omega\text{m}227.27 Ωm.
b) What is the difference between a zener diode and a conventional p n p n p-np-npn junction diode? Explain the breakdown processes observed in case of zener diode.
Answer:
The main difference between a Zener diode and a conventional p n p n p-np-npn junction diode lies in their breakdown mechanisms and the way they are used in circuits:
  1. Conventional p n p n p-np-npn Junction Diode:
    • A conventional diode is designed to allow current to flow in one direction (forward bias) and block it in the opposite direction (reverse bias).
    • When reverse-biased, a conventional diode experiences a small leakage current until the reverse voltage reaches a critical value called the breakdown voltage. Beyond this voltage, the diode undergoes avalanche breakdown, which can cause permanent damage if the current is not limited.
  2. Zener Diode:
    • A Zener diode is specifically designed to operate in the reverse breakdown region without being damaged.
    • It has a precisely controlled breakdown voltage, known as the Zener voltage ( V Z V Z V_(Z)V_ZVZ), at which it starts conducting in the reverse direction.
    • Zener diodes are used for voltage regulation and as reference voltages in circuits.
Breakdown Processes in Zener Diode:
There are two primary breakdown mechanisms observed in a Zener diode:
  1. Zener Breakdown: This occurs in diodes with a low breakdown voltage (typically less than 5V). At the Zener voltage, the strong electric field in the depletion region causes a significant increase in the tunneling of electrons through the energy barrier, leading to a sharp increase in reverse current. This process is not destructive, and the diode can return to its normal state once the voltage is reduced.
  2. Avalanche Breakdown: This occurs in diodes with higher breakdown voltages (typically above 5V). When the reverse bias voltage increases, it accelerates the minority carriers to high velocities. These carriers then collide with the lattice atoms, creating additional electron-hole pairs, leading to a chain reaction and a sudden increase in reverse current. Like Zener breakdown, avalanche breakdown is not destructive, and the diode can return to normal operation when the voltage is lowered.
In summary, the key difference between a Zener diode and a conventional diode is their ability to operate safely in the reverse breakdown region, with the Zener diode being specifically designed for this purpose. The breakdown mechanism in a Zener diode can be either Zener breakdown or avalanche breakdown, depending on the breakdown voltage.
  1. a) Draw the structure of an n-channel JFET and explain the process of pinch-off when appropriate voltage bias is applied. Why is the depletion layer wider near the drain terminal?
Answer:
An n-channel JFET (Junction Field-Effect Transistor) consists of a channel of n-type semiconductor material through which current flows, with p-type material regions on either side forming the gate. The source and drain terminals are at the ends of the n-channel, while the gate terminal is connected to the p-type regions.
Structure of an n-channel JFET:
original image
Process of Pinch-Off:
  1. Initial State: When no voltage is applied between the gate and source (V_GS = 0), the n-channel is wide open, and electrons can flow freely from the source to the drain.
  2. Applying V_GS: As a negative voltage is applied between the gate and source (V_GS < 0), a depletion region forms around the p-n junctions, narrowing the n-channel. This reduces the current flow from source to drain.
  3. Pinch-Off: As V_GS is made more negative, the depletion region extends further into the n-channel, eventually "pinching off" the channel near the drain. At this point, the JFET enters the saturation region, where the current becomes constant and independent of the drain-source voltage (V_DS). The pinch-off voltage (V_P) is the gate-source voltage at which the channel is completely pinched off.
Wider Depletion Layer Near the Drain Terminal:
The depletion layer is wider near the drain terminal because the drain-source voltage (V_DS) adds to the gate-source voltage (V_GS) in reverse-biasing the gate-drain junction. As the drain is more positive than the source, the electric field is stronger near the drain, causing a wider depletion region. This effect is more pronounced as V_DS increases, leading to a tapered channel shape with a narrower opening near the drain. This phenomenon is crucial for the operation of the JFET, as it helps in controlling the current flow through the device.

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\(cos\left(2\theta \right)=cos^2\theta -sin^2\theta \)

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